1. Field of the Invention
The present invention relates, in general, to semiconductor packages and, more particularly, but not by way of limitation, to a semiconductor package that can accommodate a larger semiconductor chip without increasing the foot print area afforded to a conventional semiconductor package. Additionally, the present invention relates to a semiconductor package having an increased moisture path.
2. History of Related Art
It is conventional in the electronic industry to encapsulate one or more semiconductor devices, such as integrated circuit dies, or chips, in a semiconductor package. These plastic packages protect a chip from environmental hazards, and provide a method of and apparatus for electrically and mechanically attaching the chip to an intended device. Recently, such semiconductor packages have included metal lead frames for supporting an integrated circuit chip which is bonded to a chip paddle region formed centrally therein. Bond wires which electrically connect pads on the integrated circuit chip to individual leads of the lead frame are then incorporated. A hard plastic encapsulating material, or encapsulate, which covers the bond wire, the integrated circuit chip and other components, forms the exterior of the package. A primary focus in this design is to provide the chip with adequate protection from the external environment in a reliable and effective manner.
As set forth above, the semiconductor package herein described incorporates a lead frame as the central supporting structure of such a package A portion of the lead frame completely surrounded by the plastic encapsulate is internal to the package Portions of the lead frame extend internally from the package and are then used to connect the package externally. More information relative to lead frame technology may be found in Chapter 8 of the book Micro Electronics Packaging Handbook, (1989), edited by R. Tummala and E. Rymaszewski, incorporated by reference herein. This book is published by Van Nostrand Reinhold, 115 Fifth Avenue, New York, N.Y.
Once the integrated circuit chips have been produced and encapsulated in semiconductor packages described above, they may be used in a wide variety of electronic appliances. The variety of electronic devices utilizing semiconductor packages has grown dramatically in recent years. These devices include cellular phones, portable computers, etc. Each of these devices typically include a motherboard on which a significant number of such semiconductor packages are secured to provide multiple electronic functions. These electronic appliances are typically manufactured in reduced sizes and at reduced costs, which results in increased consumer demand. Accordingly, not only are semiconductor chips highly integrated, but also semiconductor packages are highly miniaturized with an increased level of package mounting density.
According to such miniaturization tendencies, semiconductor packages, which transmit electrical signals from semiconductor chips to motherboards and support the semiconductor chips on the motherboards, have been designed to have a small size. By way of example only, such semiconductor packages may have a size on the order of 1xc3x971 mm to 10xc3x9710 mm. Examples of such semiconductor packages are referred to as MLF (micro leadframe) type semiconductor packages and MLP (micro leadframe package) type semiconductor packages. Both MLF type semiconductor packages and MLP type semiconductor packages are generally manufactured in the same manner.
A micro electronic circuit with a significant number of semiconductor chips is designed to conduct multiple functions in a minimal period of time. Additionally, semiconductor packages have become increasingly miniaturized with an increase in semiconductor package mounting density.
Demand for higher-speed, slimmer, and multi-functional electric appliances has lead to the development of semiconductor chips that have a high memory capacity without increasing thickness of the semiconductor chip. However, to achieve high memory capacity, the semiconductor chips must have an increased size. Therefore, to utilize slim semiconductor packages with multi-pins, there is a need for a technique of mounting the larger semiconductor packages.
A conventional small outline integrated circuit (SOIC) type semiconductor package is a surface-mounting type semiconductor package Other types include a small outline J-bend (SOJ) type, a small outline package (SOP) type, and a quad flat package (QFF) type semiconductor package. Similar in structure to the SOIC type, these semiconductor packages differ from one to another only in the bend shape.
An SOIC type semiconductor package comprises a semiconductor chip, which has a plurality of bond pads on its upper surface along its perimeter, and a chip paddle that is bonded to the bottom surface of the semiconductor chip via a conductive or non-conductive adhesive. A plurality of internal leads are arranged at regular intervals along the opposite sides of the semiconductor chip. External leads, which are bent in a seagull wing shape, are extended from the internal leads. Via conductive wires, such as gold or aluminum wires, bond pads of the semiconductor chip are electrically connected to the internal leads.
The semiconductor chip, the chip paddle, the conductive wires and the internal leads are encapsulated by an encapsulation material, such as an epoxy resin or resinous encapsulation material, to create a package body that has the function of preventing the internal components from being damaged by external factors, such as dust, heat, moisture, electrical and mechanical loads, etc. Typically, the chip paddle, the internal leads and the external leads are made of copper (Cu) or alloy, collectively composing a leadframe.
While an area of the upper surface of the internal lead is plated with copper (Cu) to improve the bonding strength with the conductive wires, an area of the external lead, which is to be fused onto a motherboard by soldering, is plated with nickel (Ni), tin (Sn), or palladium (Pd).
As described above, the conventional semiconductor package, in which the chip paddle occupies a larger space than does the semiconductor chip, has such a structure that results in difficulties with regard to securing a space for a large-size semiconductor chip. This is because the internal leads are spaced at regular intervals from each other and at a predetermined distance from the chip paddle.
Additionally, the internal leads formed in the semiconductor package are further extended over the package body from its front and rear sides or its front, rear, left and right sides. Thus, when such a semiconductor package is mounted on a motherboard, the semiconductor package occupies a significantly large space, which results in a decreased packaging density as well as adversely affecting design tolerance of electric patterns.
Further, when a large-size semiconductor chip is mounted in a semiconductor package of such a structure, the semiconductor package must be enlarged, which decreases packaging density as well as increasing the size of the motherboard to accommodate the larger semiconductor chip. Thus, the motherboard""s foot print area to which the external leads of the semiconductor package are fused must be re-designed.
A further drawback of conventional semiconductor chip design is that the semiconductor chip is completely encapsulated within a package body formed of a resinous material, which results in a very poor heat radiation ability.
The present invention relates to semiconductor packages that can accommodate a larger semiconductor chip. More particularly, one aspect of an embodiment of the present invention includes a semiconductor package comprising a semiconductor chip having a plurality of bond pads on its upper surface, a chip paddle bonded to the bottom surface of the semiconductor chip via an adhesive, and a plurality of leads, each having a lead etched part at the end facing the chip paddle. The leads are formed at regular intervals along the perimeter of the chip paddle. Conductive wires electrically connect the bond pads of the semiconductor chip to the leads. A package body houses the semiconductor chip, the conductive wires, the chip paddle and the leads, which are encapsulated by an encapsulation material while the chip paddle and the leads are externally exposed at their side surfaces and bottom surfaces. In one embodiment of the present invention, a lower side area of the chip paddle is etched to the extent that the resulting paddle etched part amounts to 10-90% of the total area of the lower side area with preference to a location at the inside of the lower side area of the chip paddle. While the chip paddle and the lower surfaces of the leads are preferably in a common plane, the chip paddle may be thicker than the leads.
In another aspect, the semiconductor package of the present invention has a noticeable advantage over conventional SOIC type semiconductor packages, in that the semiconductor of the present invention can use a 3.5 folds larger semiconductor chip with the same volume as that of the conventional type semiconductor packages. In addition, in the semiconductor package of the present invention, the bottom surface of the lead, i.e., the position at which lands are formed, may be the same position at which the external leads are fused to the motherboard, so that a conventional foot print area can be utilized Therefore, no design modification on the motherboard is required.
Moreover, the semiconductor package of the present invention shows excellent heat radiation due to its bottom surface being exposed to the outside. Further, the paddle etched part formed in the chip paddle brings about a remarkable improvement in the locking force between the chip paddle and the package body and in the fluidity of an encapsulation material during an encapsulation process. Additionally, the passage through which moisture permeates the semiconductor package is lengthened to minimize the influence of moisture on the semiconductor package. Typically, moisture permeates a semiconductor package at the interface between the encapsulate material and an exposed component, such as the chip paddle.